View PCA6107_545832.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
www.ti.com
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
FEATURES
* * * * * * * * * * * * Low Standby Current Consumption of 1 A Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Active-Low Reset Input Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant I/O Ports 400-kHz Fast I2C Bus Three Hardware Address Pins Allow for Use of up to Eight Devices on the I2C/SMBus Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset High-Impedance Open Drain on P0 * * * * * * Power Up With All Channels Configured as Inputs No Glitch On Power Up Noise Filter on SCL/SDA Inputs Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101)
DW PACKAGE (TOP VIEW)
INT SCL SDA A0 A1 A2 P0 P1 GND
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VCC VCC RESET P7 P6 P5 P4 P3 P2
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)]. The PCA6107 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. ORDERING INFORMATION
TA -40C to 85C SOIC - DW PACKAGE (1) Tube of 40 Reel of 2000 Reel of 250 (1) ORDERABLE PART NUMBER PCA6107DW PCA6107DWR PCA6107DWT PCA6107 TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2006, Texas Instruments Incorporated
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The system master can reset the PCA6107 in the event of a timeout or other improper operation by asserting a low in the active-low reset (RESET) input. The power-on reset puts the registers in their default states and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part. The PCA6107 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA6107 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption and a high-impedance open-drain output pin, P0. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight devices to share the same I2C bus or SMBus. TERMINAL FUNCTIONS
TERMINAL NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME INT SCL SDA A0 A1 A2 P0 P1 GND P2 P3 P4 P5 P6 P7 RESET VCC VCC DESCRIPTION Interrupt output. Connect to VCC through a pullup resistor. Serial clock bus. Connect to VCC through a pullup resistor. Serial data bus. Connect to VCC through a pullup resistor. Address input. Connect directly to VCC or ground. Address input. Connect directly to VCC or ground. Address input. Connect directly to VCC or ground. P-port open-drain input/output. Connect to VCC through a pullup resistor. P-port input/output Ground P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output P-port input/output Active-low reset input. Connect to VCC through a pullup resistor if no active connection is used. Supply voltage Supply voltage
2
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
INT
1
Interrupt Logic
LP Filter
A0 A1 A2 SCL SDA
4 5 6 2 3 Input Filter I2C Bus Control Shift Register 8 Bits I/O Port P7-P0
Write Pulse VCC RESET GND 17, 18 16 9 Power-On Reset Read Pulse
A.
All I/Os are set to inputs at reset.
3
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
SIMPLIFIED SCHEMATIC OF P0
Data From Shift Register Data From Shift Register Write Configuration Pulse Write Pulse Configuration Register
D FF Q
Output Port Register Data
D FF Q
CK Q
P0 ESD Protection Diode Input Port Register
D Q FF
CK Q Output Port Register
GND Input Port Register Data
Read Pulse
CK Q
Data From Shift Register Write Polarity Pulse
D
Q FF
Polarity Register Data
CK Q Polarity Inversion Register
A.
On power up or reset, all registers return to default values.
4
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
SIMPLIFIED SCHEMATIC OF P1 TO P7
Data From Shift Register Data From Shift Register Write Configuration Pulse Write Pulse
Configuration Register D Q FF CK Q D Q FF
Output Port Register Data VCC
P1 to P7 ESD Protection Diode Input Port Register D Q FF GND Input Port Register Data
CK Q Output Port Register
Read Pulse
CK Q
Data From Shift Register Write Polarity Pulse
D
Q FF
Polarity Register Data
CK Q Polarity Inversion Register
A.
On power up or reset, all registers return to default values.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0-A2) of the slave device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation.
5
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S Start Condition
P Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL Data Line Change
Figure 2. Bit Transfer
Data Output by Transmitter
NACK Data Output by Receiver
ACK
SCL From Master S Start Condition
1
2
8
9
Clock Pulse for Acknowledgment
Figure 3. Acknowledgment on the I2C Bus Interface Definition
BYTE I2C slave address Px I/O data bus BIT 7 (MSB) L P7 6 L P6 5 H P5 4 H P4 3 A2 P3 2 A1 P2 1 A0 P1 0 (LSB) R/W P0
6
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
Device Address
The address of the PCA6107 is shown in Figure 4.
Slave Address 0 0 1 1 A2 A1 A0 R/W Programmable
Fixed
Figure 4. PCA6107 Address Address Reference
INPUTS A2 L L L L H H H H A1 L L H H L L H H A0 L H L H L H L H I2C BUS SLAVE ADDRESS 24 (decimal), 18 (hexadecimal) 25 (decimal), 19 (hexadecimal) 26 (decimal), 1A (hexadecimal) 27 (decimal), 1B (hexadecimal) 28 (decimal), 1C (hexadecimal) 29 (decimal), 1D (hexadecimal) 30 (decimal), 1E (hexadecimal) 31 (decimal), 1F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA6107. Two bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a new command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.
0 0 0 0 0 0 B1 B0
Figure 5. Control Register Bits Command Byte
CONTROL REGISTER BITS B1 0 0 1 1 B0 0 1 0 1 COMMAND BYTE (HEX) 0x00 0x01 0x02 0x03 REGISTER Input Port Output Port Polarity Inversion Configuration PROTOCOL Read byte Read/write byte Read/write byte Read/write byte POWER-UP DEFAULT xxxx xxxx 0000 0000 1111 0000 1111 1111
7
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It acts only on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next. Register 0 (Input Port Register)
BIT DEFAULT I7 X I6 X I5 X I4 X I3 X I2 X I1 X I0 X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Register 1 (Output Port Register)
BIT DEFAULT O7 0 O6 0 O5 0 O4 0 O3 0 O2 0 O1 0 O0 0
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. Register 2 (Polarity Inversion Register)
BIT DEFAULT N7 1 N6 1 N5 1 N4 1 N3 0 N2 0 N1 0 N0 0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Register 3 (Configuration Register)
BIT DEFAULT C7 1 C6 1 C5 1 C4 1 C3 1 C2 1 C1 1 C0 1
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA6107 in a reset condition until VCC has reached VPOR. At that time, the reset condition is released, and the PCA6107 registers and I2C/SMBus state machine initializes to their default states. After that, VCC must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. The RESET input can be asserted to reset the system, while keeping the VCC at its operating level.
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA6107 registers and I2C/SMBus state machine are held in their default states until the RESET input is again high. This input requires a pullup resistor to VCC, if no active connection is used.
8
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port Register. The INT output has an open-drain structure and requires pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and PCA6107 through write and read commands. Writes Data is transmitted to the PCA6107 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission.
SCL 1 2 3 4 5 6 7 8 9 Command Byte A 0 0 0 0 0 0 0 1 A Data to Port Data 1 A P
Slave Address SDA S 0 0 1 1 A2 A1 A0 0
Start Condition Write to Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
Data Out From Port tpv
Data 1 Valid
Figure 6. Write to Output Port Register

SCL
1
2
3
4
5
6
7
8
9 Command Byte A 0 0 0 0 0 0 0 1/0 A Data to Register Data A P
Slave Address SDA S 0 0 1 1 A2 A1 A0 0 R/W
Start Condition
ACK From Slave
ACK From Slave
ACK From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
9
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
Reads The bus master first must send the PCA6107 address with the least-significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA6107 (see Figure 8 and Figure 9). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.
Slave Address S0 0 1 ACK From Slave A Command Byte ACK From Slave AS0 Slave Address 0 1 ACK From ACK From Master Slave Data from Register Data First byte A
1 A2 A1 A0 0 R/W
1 A2 A1 A0 1 A R/W
At this moment, master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter
Data from Register Data Last Byte
NACK From Master NA P
Figure 8. Read From Register

SCL
1
2
3
4
5
6
7
8
9 Data From Port A ACK From Slave Data 1 A ACK From Master Data From Port Data 4 NA P NACK From Master Stop Condition
Slave Address SDA S0 0 1 1 A2 A1 A0 0 R/W
Start Condition Read From Port Data Into Port
Data 2 tph
Data 3 tps
Data 4
Data 5
INT tiv tir
A. B. C.
This figure assumes the command byte has been programmed previously with 00h. Transfer of data can be stopped at any moment by a Stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register
10
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006 (1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO IIK IOK IIOK IOL IOH ICC JA Tstg (1) (2) (3) Supply voltage range Input voltage range (2) Output voltage range (2) VI < 0 VO < 0 VO < 0 or VO > VCC VO = 0 to VCC VO = 0 to VCC Input clamp current Output clamp current Input/output clamp current Continuous output low current Continuous output high current, P7-P1 Continuous current through GND Continuous current through VCC Package thermal impedance (3) Storage temperature range -65 -0.5 -0.5 -0.5 MAX 6 6 6 -20 -20 20 50 -50 -200 160 73 150 UNIT V V V mA mA mA mA mA mA C/W C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature SCL, SDA A2-A0, P7-P0, RESET SCL, SDA A2-A0, P7-P0, RESET P7-P1 P7-P0 -40 2.3 0.7 x VCC 2 -0.5 -0.5 MAX 5.5 5.5 5.5 0.3 x VCC 0.8 -10 25 85 UNIT V V V mA mA C
11
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VPOR Input diode clamp voltage Power-on reset voltage TEST CONDITIONS II = -18 mA VI = VCC or GND, IO = 0 VCC 2.3 V to 5.5 V VPOR 2.3 V IOH = -8 mA VOH P-port high-level output voltage (2) IOH = -10 mA 3V 4.5 V 4.75 V 2.3 V 3V 4.5 V 4.75 V SDA IOL P port (3) VOL = 0.4 V VOL = 0.5 V VOL = 0.55 V VOL = 0.7 V INT P port, except for IOH P0 (3) SCL, SDA A2-A0, RESET P port P port P0 (3) VOL = 0.4 V VOH = VCC - 0.4 V VOH = 4.6 V VOH = 3.3 V VI = VCC or GND VI = VCC VI = GND VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz Operating mode ICC VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 100 kHz 2.3 V to 5.5 V 2.3 V to 5.5 V 4.6 V to 5.5 V 3.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 5.5 V 3.6 V 2.7 V 5.5 V 3.6 V 2.7 V 5.5 V Standby mode VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 0 kHz One input at VCC - 0.6 V, Other inputs at VCC or GND Every LED I/O at VI = 4.3 V, fSCL = 0 kHz VI = VCC or GND VIO = VCC or GND 3.6 V 2.7 V 2.3 V to 5.5 V 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V 4 5.5 7.5 19 12 8 1.5 1 0.6 0.25 0.25 0.2 2.3 V to 5.5 V 2.3 V to 5.5 V 1.8 2.6 3 4.1 1.5 2.5 3 4 3 8 8 10 3 -4 1 1 1 1 1 1 25 22 20 5 4 3 1 0.9 0.8 0.2 mA 0.4 6 8 9.5 pF pF A mA A A A A 20 20 24 mA V MIN -1.2 1.65 2.1 TYP (1) MAX UNIT V V
II IIH IIL
ICC
Additional current in Standby mode
CI Cio (1) (2) (3)
SCL SDA P port
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7-P1) must be limited to a maximum current of 100 mA. The total current sourced by all I/Os must be limited to 85 mA per bit.
12
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE I2C BUS MIN fscl tsch tscl tsp tsds tsdh ticr ticf tocf tbuf tsts tsth tsps tvd(data) tvd(ack) Cb (1) I2C clock frequency I2C clock high time I2C clock low time I2C spike time 250 0 1000 300 300 4.7 4.7 4 4 1 1 400 20 + 0.1Cb I2C serial data setup time I2C serial data hold time I2C input rise time I2C input fall time I2C output fall time (10-pF to 400-pF bus) I2C bus free time between Stop and Start I2C Start or repeater Start condition setup time I2C Start or repeater Start condition hold time I2C Stop condition setup time Valid data time; SCL low to SDA output valid Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low I2C bus capacitive load Cb = total capacitance of one bus line in pF 0 4 4.7 50 100 0 20 + 0.1Cb (1)
(1)
FAST MODE I2C BUS MIN 0 0.6 1.3 50 MAX 400
UNIT kHz s s ns ns ns 300 300 300 ns ns ns s s s s 0.9 0.9 400 s s pF
MAX 100
20 + 0.1Cb (1) 1.3 0.6 0.6 0.6
Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE I2C BUS MIN tW tREC tRESET (1) Reset pulse duration Reset recovery time Time to reset (1) 16 0 400 MAX FAST MODE I2C BUS MIN 16 0 400 MAX ns ns ns UNIT
The PCA6107 requires a minimum of 400 ns to be reset.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
PARAMETER tiv tir tpv tps tph Interrupt valid time Interrupt reset delay time Output data valid Input data setup time Input data hold time FROM P port SCL SCL SCL P port P port TO INT INT P0 P1-P7 SCL SCL 0 200 STANDARD MODE I2C BUS MIN MAX 4 4 250 200 0 200 FAST MODE I2C BUS MIN MAX 4 4 250 200 s s ns ns ns UNIT
13
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs TEMPERATURE
60 55 50 VCC = 5 V f SCL = 400 kHz I/Os unloaded
STANDBY SUPPLY CURRENT vs TEMPERATURE
20 SCL = VCC
70 60
SUPPLY CURRENT vs SUPPLY VOLTAGE
ICC - Standby Supply Current - nA
f SCL = 400 kHz I/Os unloaded
ICC - Supply Current - A
0 25 50 75 100
ICC - Supply Current - A
45 40 35 30 25 20 15 10 5
15 VCC = 5 V 10 VCC = 3.3 V 5 VCC = 2.5 V
50 40 30 20 10 0
VCC = 3.3 V
VCC = 2.5 V
0 -50
-25
0
25
50
75
100
0 -50
-25
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
VCC - Supply Voltage - V
I/O SINK CURRENT vs OUTPUT LOW VOLTAGE
30 VCC = 2.5 V 25
40
I/O SINK CURRENT vs OUTPUT LOW VOLTAGE
50
I/O SINK CURRENT vs OUTPUT LOW VOLTAGE
VCC = 3.3 V 35
45 ISINK - I/O Sink Current - mA 40 35 30 25 20 15 10 5 0 0.0
VCC = 5 V TA = -40C
ISINK - I/O Sink Current - mA
ISINK - I/O Sink Current - mA
TA = -40C 20 TA = 25C 15 10 TA = 85C 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 VOL - Output Low Voltage - V
30 25 TA = 25C 20 15 10 5 0 0.0 0.1 0.2
TA = -40C
TA = 25C
TA = 85C
TA = 85C
0.3
0.4
0.5
0.6
0.1
0.2
0.3
0.4
0.5
0.6
VOL - Output Low Voltage - V
VOL - Output Low Voltage - V
I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE (P7-P1)
20 VCC = 2.5 V
30
I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE (P7-P1)
40
I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE (P7-P1)
VCC = 3.3 V
VCC = 5 V 35 ISOURCE - I/O Source Current - mA TA = -40C
ISOURCE - I/O Source Current - mA
ISOURCE - I/O Source Current - mA
25 TA = -40C 20 TA = 25C
15
TA = -40C
30 25 20 15 10 5 0 TA = 25C
TA = 25C 10
15
10 5 TA = 85C
5
TA = 85C
TA = 85C
0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (VCC - VOH) - Output High Voltage - V
0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (VCC - VOH) - Output High Voltage - V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC - VOH) - Output High Voltage - V
14
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE (P7-P1)
6
OUTPUT HIGH VOLTAGE vs TEMPERATURE (P7-P1)
600
300
OUTPUT LOW VOLTAGE vs TEMPERATURE
(VCC - VOH) - Output High Voltage - mV
TA = 25C 5
550 500 450 400 350 300 250 200 150 100 50
VCC = 2.5 V, ISOURCE = 10
275
VCC = 2.5 V, ISINK = 10 mA
VOL - Output Low Voltage - mV
250 225 200 175 150 125 100 75 50 25 VCC = 2.5 V, ISINK = 1 mA VCC = 5 V, ISINK = 1 mA VCC = 5 V, ISINK = 10 mA
VOH - Output High Voltage - V
4 IOH = -4 mA 3 IOH = -8 mA IOH = -10 mA 1
VCC = 5 V, ISOURCE = 10
2
VCC = 2.5 V, ISOURCE = 1 mA VCC = 5 V, ISOURCE = 1 mA
0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VCC - Supply Voltage - V
0 -50
-25
0
25
50
75
100
0 -50
-25
0
25
50
75
100
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
15
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 k DUT SDA CL = 50 pF (see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) tscl tsch 0.7 x VCC SCL ticr tbuf SDA ticf tsth Start or Repeat Start Condition VOLTAGE WAVEFORMS ticr tsds tsdh Repeat Start Condition tsps Stop Condition ticf tsp tPHL tPLH 0.7 x VCC 0.3 x VCC tsts 0.3 x VCC Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 07 (MSB) Data Bit 10 (LSB) Stop Condition (P)
BYTE 1 2, 3
DESCRIPTION I2C address P-port data
A. B. C.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
16
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 k DUT INT CL = 100 pF (see Note A)
INTERRUPT LOAD CONFIGURATION
ACK From Slave Start Condition Slave Address S 0 0 1 1 A2 A1 A0 1 A R/W 8 Bits (One Data Bytes) From Port Data 1
ACK From Slave Data From Port A Data 2 1 P
1
2
3
4
5
6
7
8
A
A
tir
tir
B B
INT A A Data Into Port Address Data 1 tsps
tiv
Data 2
0.7 x VCC INT 0.3 x VCC tiv 0.7 x VCC 0.3 x VCC View A-A
SCL
0.7 x VCC R/W A 0.3 x VCC tir
Pn
INT
0.7 x VCC 1.5 V 0.3 x VCC View B-B
A. B. C.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR = 10 MHz, ZO = 50 , tr/tf 30 ns. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
17
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Pn DUT CL = 50 pF (see Note A) 500 W 500 W 2 x VCC
P-PORT LOAD CONFIGURATION
SCL
0.7 x VCC P0 A Slave ACK P7 0.3 x VCC
SDA tpv (see Note B)
Pn
WRITE MODE (R/W = 0)
SCL
P0 tps
Pn
READ MODE (R/W = 1)
A. B. C. D. E.
CL includes probe and jig capacitance. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
18

A
Unstable Data
Last Stable Bit
0.7 x VCC P7 tph 0.7 x VCC 1.5 V 0.3 x VCC 0.3 x VCC
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 1 k DUT SDA CL = 50 pF (see Note A) DUT
Pn
500 W CL = 50 pF (see Note A)
2 x VCC
500 W
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start SCL ACK or Read Cycle
SDA
0.3 y VCC tRESET
RESET tREC tw Pn
VCC/2
VCC/2 tRESET
A. B. C. D.
CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
19
PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
www.ti.com
APPLICATION INFORMATION
Figure 14 shows an application where the PCA6107 can be used.
VCC (5 V) VCC SCL Master Controller SDA RESET INT GND 620 1.8 k 1.8 k 2k 2k 2k SCL SDA P1 RESET P2 INT P3 PCA6107 P4 P5 A2 A1 A0 P6 ENABLE P7 B A Controlled Switch (e.g., CBT Device) RESET Subsystem 2 (e.g., Counter) VCC P0 Subsystem 1 INT 100 k (y5)
GND
ALARM Subsystem 3 (e.g., Alarm System)
VCC
A. B. C. D.
Device address is configured as 0011100 for this example. P1, P4, and P5 are configured as inputs. P0, P2, and P3 are configured as outputs. P6 and P7 are not used and must be configured as outputs.
Figure 14. Typical Application
20
www.ti.com
PCA6107 REMOTE 8-BIT AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS I2C
SCPS139A - JANUARY 2006 - REVISED JANUARY 2006
APPLICATION INFORMATION (continued) Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pin greater than or equal to VCC when the LED is off. Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when the LED is off.
VCC
LED VCC Pn
100 kW
Figure 15. High-Value Resistor in Parallel With the LED
3.3 V 5V
VCC Pn
LED
Figure 16. Device Supplied by a Low Voltage
21
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2006
PACKAGING INFORMATION
Orderable Device PCA6107DW PCA6107DWG4 PCA6107DWR PCA6107DWRG4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC
Package Drawing DW DW DW DW
Pins Package Eco Plan (2) Qty 18 18 18 18 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1YEAR Level-2-260C-1YEAR Level-2-260C-1YEAR Level-2-260C-1YEAR
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Low Power Wireless www.ti.com/lpw

▲Up To Search▲

Price & Availability of PCA6107

	To Download PCA6107 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .